Method of operating a solid state power amplifying device

ABSTRACT

According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device, an input impedance matching circuit and an output impedance matching circuit coupled to the solid state amplifying device. The input impedance matching circuit includes an input pitchfork trace pattern. The output impedance matching circuit includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit and an output bias circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation application of prior application Ser. No. 09/590,771, filed Jun. 8, 2000, entitled “A Method of Operating a Solid State Power Amplifying Device” which is assigned to the assignee of the present application.

FIELD OF THE INVENTION

[0002] This invention relates generally to the field of current-controlled solid-state power amplifying devices including, but not limited to, bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs).

BACKGROUND

[0003] It is widely known that improving output current balance of the die within solid-state, power amplifying devices results in performance improvement of gain, efficiency, peak output power and linearity. An area of amplifier performance enhancement that has heretofore been overlooked is the utilization and optimization of the amplifier circuit components to assist in balancing the output current distribution of the die of the amplifying device. Therefore, a method of balancing a solid state, power amplifying device is desired.

SUMMARY

[0004] According to one embodiment, a method of operating a solid state current-controlled power-amplifying device is disclosed. The method includes applying one or more circuit techniques in order to balance the output current of the solid state device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

[0006]FIG. 1 is a block diagram of one embodiment of a radio frequency amplification circuit;

[0007]FIG. 2A is a diagram of one embodiment of a radio frequency power BJT coupled to an input impedance matching circuit;

[0008]FIG. 2B is a diagram of one embodiment of a radio frequency power BJT coupled to an output impedance matching circuit;

[0009]FIG. 3A is a diagram of one embodiment of a base bias circuit coupled to a radio frequency power BJT; and

[0010]FIG. 3B is a diagram of one embodiment of a collector bias circuit coupled to a radio frequency power BJT.

DETAILED DESCRIPTION

[0011] In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

[0012]FIG. 1 is a block diagram of one embodiment of a radio frequency amplification circuit 100. Circuit 100 includes an input impedance matching circuit 110, an output impedance matching circuit 120, a radio frequency (RF) power bipolar junction transistor (BJT) 140, a base bias circuit 170 and a collector bias circuit 180. According to one embodiment, circuit 100 receives input RF signals at input impedance matching circuit 110, amplifies the signal and transmits the amplified signal from output impedance matching circuit 120 to a load (not shown). In other embodiments, BJT 140 may comprise other solid state amplifying devices (e.g., HBT).

Input Impedance Matching Circuit

[0013] As described above, input impedance matching circuit 110 is designed to receive RF signals. According to one embodiment, the impedance at the interface between the RF input and input impedance matching circuit 110 is 50 Ω. Input impedance matching circuit 110 transforms the impedance from the level of the RF input to the impedance of BJT 140. FIG. 2A is a diagram of BJT 140 coupled to input impedance matching circuit 110.

[0014] Referring to FIG. 2A, input impedance matching circuit 110 includes a multi-section “pitchfork feed” 220. According to one embodiment, pitchfork feed 220 is a printed trace that is configured to provide a balanced current feed into BJT 140. Typical printed traces are relatively wide single lines that feed BJT 140. However, whenever circuit 100 is operating at high frequency there is typically a higher current density towards the outside edges of the wide single trace. Such an occurrence results in an unbalanced current feed into BJT 140. Therefore, pitchfork feed 220 provides for balanced current flow into BJT 140 by evenly dividing the current across multiple connected traces resulting in a more uniform current distribution at the input of BJT 140.

[0015] Input impedance matching circuit 110 also includes series resistors 230 within branches of the pitchfork feed 220 traces. Resistors 230 further equalize the current paths into BJT 140 so that the current will not prefer one side of the pitchfork feed 220 to the others. In addition, resistors 230 reduce the likelihood of low frequency oscillation of the high frequency BJT 140. According to one embodiment, each resistor 230 has a 4.7 Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.

[0016] Input impedance matching circuit 110 further includes resistors 235. Resistors 235 are placed pairs of branches of pitchfork feed 220 to further equalize the current between any two branches of pitchfork feed 220. For example, imbalances between the top two branches of pitchfork feed 220 are reduced by the resistor 235 between the two. According to one embodiment, each resistor 230 has a 10 Ω resistance. Nevertheless, one of ordinary skill in the art will appreciate that other values for resistors 230 may be used.

Output Impedance Matching Circuit

[0017] Output impedance matching circuit 120 is coupled to BJT 140. Output impedance matching circuit 120 transforms the impedance from the level of BJT 140 to the impedance level of load coupled to circuit 100. According to one embodiment, the impedance at the interface between output impedance matching circuit 120 and the load is 50 Ω. FIG. 2B is a diagram of BJT 140 coupled to output impedance matching circuit 120.

[0018] Referring to FIG. 2B, output impedance matching circuit 120 includes a multi-section pitchfork feed 260 similar to pitchfork feed 220 in input impedance matching circuit 110. In addition to the advantages described above, the pitchfork feed 260 configuration in output impedance matching circuit 120 also presents a low impedance at the second and third harmonic frequencies to the output of BJT 140. The low impedance at the harmonic frequencies minimizes the RF voltage peaks at the output of BJT 140.

Base Bias Circuit

[0019] Base bias circuit 170 connects a power supply voltage to BJT 140 without having an affect on the RF signal amplified by BJT 140. According to one embodiment, base bias circuit 170 presents a low impedance, resistive load to the bases of BJT 140 at frequencies from 1 MHz to one-third of the operating RF frequency of BJT 140. In addition, base bias circuit 170 delivers the appropriate amount of DC current to the base of BJT 140 to optimize RF performance. FIG. 3A is a diagram of one embodiment of base bias circuit 170 coupled to BJT 140. According to one embodiment, bias circuit 170 includes a set of resistors. The resistors are coupled between a supply voltage (V_(BB)) and the base of BJT 140.

Collector Bias Circuit

[0020] Collector bias circuit 180 connects a DC power supply voltage to BJT 140 without affecting the RF signal amplified by BJT 140. According to one embodiment, bias circuit 180 results in uniform voltage across the entire lead 270 of BJT 140 coupled to the collectors of transistor 240. FIG. 3B is a diagram of one embodiment of collector bias circuit 180 coupled to BJT 140. Bias circuit 180 includes a transient voltage suppressor 310, a capacitor (C) and an inductor (L). Transient voltage suppressor 310 is connected between a supply voltage (V_(CC)) and ground.

[0021] According to one embodiment, V_(CC) supplies 45-50 volts DC at 10A to the collector of BJT 140. Transient voltage suppressor 110 suppresses voltage spikes within circuit 100 caused during the switching between high and low current levels. In one embodiment, transient voltage suppressor 110 is implemented using a diode. However, one of ordinary skill in the art will appreciate that other fast voltage clipping devices may be used to implement transient voltage suppressor 110.

[0022] Inductor L is coupled between the supply voltage and BJT 140. Inductor L provides a predetermined impedance value that prevents RF current flow from BJT 140 through bias circuit 180. However, according to one embodiment, inductor L is designed to be sufficiently small so as to minimize voltage spikes caused by transient currents that occur due to changing current through the circuit. For example, whenever the output power of circuit 100 is quickly switched from low to high (e.g., 50 ns rise/fall time), or vice versa, the current flow through inductor L changes, resulting in a transient voltage spike. The larger the inductance of inductor L, the higher the magnitude of the voltage spike. In cases where the voltage spike is sufficiently large, severe damage to BJT 140 may occur. Therefore, the small size of inductor L and the presence of transient voltage suppressor 110 permits BJT 140 to operate at higher voltages (e.g., 50 volts).

[0023] Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention. 

What is claimed is:
 1. A method of enhancing the performance of a solid state power amplifying device, the method comprising: controlling the distribution of an electromagnetic field across a single wide input lead of the solid state power amplifying device by using a first component comprised of a plurality of narrow transmission lines coupled to the input lead of the solid state power amplifying device.
 2. The method of claim 1 further comprising compensating for the distribution of an electromagnetic field across a single wide output lead of the solid state power amplifying device by using a second component comprised of a plurality of narrow transmission lines coupled to the output lead of the solid state power amplifying device.
 3. The method of claim 1 further comprising coupling a resistor within one or more of the plurality of narrow transmission lines.
 4. The method of claim 1 further comprising coupling a resistor between two or more of the plurality of narrow transmission lines.
 5. The method of claim 1 wherein the solid state power amplifying device is a bipolar junction transistor (BJT).
 6. The method of claim 1 wherein the solid state power amplifying device is a heterojunction bipolar transistor (HBT).
 7. The method of claim 1 wherein the solid state power amplifying device is a lateral diffused metal oxide semiconductor field effect transistor (LDMOS FET).
 8. The method of claim 1 wherein the solid state power amplifying device is a vertical diffused metal oxide semiconductor field effect transistor (DMOS FET).
 9. The method of claim 1 wherein the solid state power amplifying device is a metal semiconductor field effect transistor (MES FET).
 10. The method of claim 1 wherein the solid state power amplifying device is a pseudomorphic high electron mobility field effect transistor (PHEMT FET).
 11. The method of claim 1 wherein the solid state power amplifying device is a static inductance transistor (SIT).
 12. An amplification circuit comprising: a solid state power amplifying device; and a first component, coupled to a single wide input lead of the solid state power amplifying device, having a plurality of narrow transmission lines that control the distribution of an electromagnetic field across the input lead of the solid state power amplifying device.
 13. The circuit of claim 12 further comprising: an output lead coupled to the output of the solid state power amplifying device; and a second component, coupled to the single wide output lead of the solid state power amplifying device, having a plurality of narrow transmission lines that compensate for the distribution of an electromagnetic field across the output lead of the solid state power amplifying device.
 14. The circuit of claim 12 further comprising a resistor coupled within one or more of the plurality of narrow transmission lines of the first component.
 15. The circuit of claim 12 further comprising a resistor coupled between two or more of the plurality of narrow transmission lines of the first component.
 16. The circuit of claim 12 further comprising: a radio frequency source coupled to the input of the first component; and a load coupled to the output of the second component.
 17. The circuit of claim 16 further comprising an output bias circuit coupled to the solid state power amplifying device.
 18. The circuit of claim 17 wherein the output bias circuit comprises a transient voltage suppressor.
 19. The circuit of claim 12 wherein the solid state power amplifying device comprises a lateral diffused metal oxide semiconductor field effect transistor (LDMOS FET).
 20. The circuit of claim 12 wherein the solid state power amplifying device comprises a vertical diffused metal oxide semiconductor field effect transistor (DMOS FET).
 21. The circuit of claim 12 wherein the solid state power amplifying device is a metal semiconductor field effect transistor (MES FET).
 22. The circuit of claim 12 wherein the solid state power amplifying device is a pseudomorphic high electron mobility field effect transistor (PHEMT FET).
 23. The circuit of claim 12 wherein the solid state power amplifying device is a static inductance transistor (SIT).
 24. The method of claim 12 wherein the solid state power amplifying device is a bipolar junction transistor (BJT).
 25. The method of claim 12 wherein the solid state power amplifying device is a heterojunction bipolar transistor (HBT). 